Award Recognizes Efforts to Improve Quality of Verilog, SystemVerilog and Verilog AMS Standards Defense News ~ NAPA, CA--(Marketwire - 02/23/10) - Accellera, the electronics industry organization focused on electronic design automation (EDA) and Intellectual Property (IP) standards, announced today that Shalom Bresticker, Senior CAD Engineer, Intel, is the 2010 recipient of its 7th annual Technical Excellence Award. The Award recognizes Mr. Bresticker's volunteer contributions to Accellera's SystemVerilog, Open Verification Library (OVL) and Verilog Analog/Mixed Signal (AMS) standards.
Accellera's chair, Shrenik Mehta, will present Accellera's Technical Excellence Award at 3pm on Wednesday, February 24, 2010, during the organization's Design and Verification Conference and Exhibition (DVCon) at the Doubletree hotel in San Jose, California before the Panel, What Keeps You Up at Night?
"Shalom Bresticker's achievements are important for the industry because they provide clarity and improve the quality of existing and future Verilog-related design and verification language standards," said Shrenik Mehta, Accellera's chair. "Because of Shalom's expertise, contributions and understanding of the language and its place in the electronic design and verification ecosystem, we have better quality standards."
Mehta continued, "Shalom has a long standing devotion to the development of a quality specification for the Verilog and SystemVerilog languages. He has scrutinized the standards at every step in the process for completeness and accuracy. Tool developers and users of the language for design and verification have better standards because of his constant attention, and devotion to producing quality standards. He is someone whom many should look to emulate."
"It is an honor to be recognized by Accellera for my work on the Verilog standard and its related language standards," added Shalom Bresticker.
About Shalom Bresticker
Shalom's in-depth knowledge of the Verilog standard and the requirements of the industry have been immensely helpful in delivering EDA standards that significantly improve silicon design quality and productivity. His thorough review of the Verilog standards and his attention to detail have significantly improved the quality of Accellera's language standards. In addition to his contributions to Verilog, Shalom reviewed the Verilog Analog Mixed-Signal (AMS) standard in order to improve Verilog AMS and Verilog standards alignment and the Verilog or IEEE 1364™ Language Reference Manual (LRM).
Since 2005, Shalom Bresticker has been a Senior CAD Engineer in Intel's LAN Access Division (LAD) in Jerusalem, Israel. In this role, he works on and supports logic design and verification tools and methodologies. Previously, he was a VLSI engineer at Motorola/Freescale Semiconductor Israel, where he was a key contributor to Motorola's Semiconductor Reuse Standards (SRS). Shalom started participating in the Verilog standards committee in 1995, has been active in the SystemVerilog, Verilog-AMS and OVL technical committees, and has edited the Verilog or IEEE 1364™ -2001 (Version C) and IEEE 1364-2005 LRMs.
Shalom earned a BSE in Electrical Engineering and Computer Science from Princeton University and an MS in Electrical Engineering from the Technion-Israel Institute of Technology.
About Accellera's Technical Excellence Award and Technical Subcommittees
Each year, Accellera's Technical Excellence Award recognizes the outstanding achievements of a Technical Subcommittee member. Candidates are nominated by the industry at large, and nominations are endorsed by participants in Accellera's Technical Subcommittees. All of Accellera Technical Subcommittee members are eligible for the award.
Accellera's Technical Subcommittees produce effective and efficient standards for today's advanced IC designs. Participation comes from Accellera member companies, industry contributors and independents. Technical contributors typically have many years of practical experience with IC design and developing and using EDA tools.
About Accellera
Accellera, an industry organization formed in 2000, provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are transferred to the IEEE standards body for formalization and ongoing change control. For more information, please visit http://www.accellera.org/.
Accellera's chair, Shrenik Mehta, will present Accellera's Technical Excellence Award at 3pm on Wednesday, February 24, 2010, during the organization's Design and Verification Conference and Exhibition (DVCon) at the Doubletree hotel in San Jose, California before the Panel, What Keeps You Up at Night?
"Shalom Bresticker's achievements are important for the industry because they provide clarity and improve the quality of existing and future Verilog-related design and verification language standards," said Shrenik Mehta, Accellera's chair. "Because of Shalom's expertise, contributions and understanding of the language and its place in the electronic design and verification ecosystem, we have better quality standards."
Mehta continued, "Shalom has a long standing devotion to the development of a quality specification for the Verilog and SystemVerilog languages. He has scrutinized the standards at every step in the process for completeness and accuracy. Tool developers and users of the language for design and verification have better standards because of his constant attention, and devotion to producing quality standards. He is someone whom many should look to emulate."
"It is an honor to be recognized by Accellera for my work on the Verilog standard and its related language standards," added Shalom Bresticker.
About Shalom Bresticker
Shalom's in-depth knowledge of the Verilog standard and the requirements of the industry have been immensely helpful in delivering EDA standards that significantly improve silicon design quality and productivity. His thorough review of the Verilog standards and his attention to detail have significantly improved the quality of Accellera's language standards. In addition to his contributions to Verilog, Shalom reviewed the Verilog Analog Mixed-Signal (AMS) standard in order to improve Verilog AMS and Verilog standards alignment and the Verilog or IEEE 1364™ Language Reference Manual (LRM).
Since 2005, Shalom Bresticker has been a Senior CAD Engineer in Intel's LAN Access Division (LAD) in Jerusalem, Israel. In this role, he works on and supports logic design and verification tools and methodologies. Previously, he was a VLSI engineer at Motorola/Freescale Semiconductor Israel, where he was a key contributor to Motorola's Semiconductor Reuse Standards (SRS). Shalom started participating in the Verilog standards committee in 1995, has been active in the SystemVerilog, Verilog-AMS and OVL technical committees, and has edited the Verilog or IEEE 1364™ -2001 (Version C) and IEEE 1364-2005 LRMs.
Shalom earned a BSE in Electrical Engineering and Computer Science from Princeton University and an MS in Electrical Engineering from the Technion-Israel Institute of Technology.
About Accellera's Technical Excellence Award and Technical Subcommittees
Each year, Accellera's Technical Excellence Award recognizes the outstanding achievements of a Technical Subcommittee member. Candidates are nominated by the industry at large, and nominations are endorsed by participants in Accellera's Technical Subcommittees. All of Accellera Technical Subcommittee members are eligible for the award.
Accellera's Technical Subcommittees produce effective and efficient standards for today's advanced IC designs. Participation comes from Accellera member companies, industry contributors and independents. Technical contributors typically have many years of practical experience with IC design and developing and using EDA tools.
About Accellera
Accellera, an industry organization formed in 2000, provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are transferred to the IEEE standards body for formalization and ongoing change control. For more information, please visit http://www.accellera.org/.
Contact:
Press Contact:
Georgia Marszalek
ValleyPR for Accellera
+650 345 7477
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